Optimal of 1-bit Comparator design and Energy Estimation using Quantum Dot Cellular Automata

Authors

  • V. Satyanarayana 1M.Tech Scholar,Department of ECE,Sree Vidyanikethan Engineering College,Tirupati https://orcid.org/0000-0002-0180-2713
  • M. Balaji M.Tech Scholar,Department of ECE,Sree Vidyanikethan Engineering College,Tirupati
  • K. Neelima M.Tech Scholar,Department of ECE,Sree Vidyanikethan Engineering College,Tirupati

Keywords:

Quantum dots, Cellular Automata, Comparator, Quantum cells, Edge computing

Abstract

Performance of CMOS technology has been affected in nanosystems due to power dissipation, area, and reliability functionalities. A research initiative which investigates other possible systems with related capacities is QCA. In this paper, QCA nanotechnology was used to create a 1-bit comparator. These circuits are easy to create and do not require any crossovers. The proposed design is extremely efficient in terms of area, cell count, quantum cost and delay, which improves the performance in the range of 74.81% to 99.87%  in terms of quantum cost. As a result, proposed designs are often found in various digital logics that require a small amount of space and low power consumption.

Downloads

Download data is not yet available.

References

A. N. Bahar and M D. Abdullah-Al-Shafi , “Optimized design and performance analysis of novel comparator and full adder in nanoscale,” Cogent Engineering, vol. 3, pp. 1-14, 2016.

Soha Maqbool Bhat, Vipan Kakkar and Suhaib Ahmed, “ Design of Efficient 1-bit Comparator in Quantum dot Cellular Automata Nano-computing, ” IEEE-HYDCON, 2020.

N. Islam, S. Waheed, & R. Akter, “Implementation of reversible logic gate in quantum dot cellular automata,” International Journal of Computer Applciations, vol. 109, pp. 41-44, 2017.

S Kumari, B. Ghosh and S. H. Gupta , “Quantum dot cellular automata magnitude comparators,” in Proc. of IEEE International Conference on Electronic Devices and Solid State Circuits (EDSSC), 2012, p. 1-2.

Heumpil Cho and Earl E. Swartzlander, “Adder Designs and Analyses for Quantum-Dot Cellular Automata” IEEE transaction on Nanotechnology, Vol. 6, No.3, May 2007, Page(s) 374-383.

K., Lent, C.S, Hennessy : Clocking of molecular quantum-dot cellular automata .J. Vacuum Sci. Technol. B: Microelectron. Nanometer Struct.19, 1752–1755 (2001).

M. R. Garg, B. Krishan , A Literature Review on Quantum Dots, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 4 (2015). 7857?7862.

Vikramkumar P, Sridharan K. Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology. Switzerland: Springer International Publishing; 2015. DOI:10.1007/978-3-319-16688-9

QCA Designer-E (2017) https://github.com/FSillT/QCA Designer Accessed 12 Mar 2019.

S. Farrokhi, K. Navi , N. Bagherzadeh, M. Hossein Moaiyeri and S. Angizi, “ Designing quantum-dot cellular automata counters with energy consumption analysis”, Microprocessors and Microsystems, vol. 39, no. 7, (2015), pp. 512-520.

X. Yin-shui and Q. Ke-ming. “Quantum Dots cellular automata comparator”. In 7th International Conference on ASIC, ASICON 2007., Page(s) 1297-1300.

Downloads

Published

2021-05-25

How to Cite

[1]
V. Satyanarayana, M. . Balaji, and K. . Neelima, “Optimal of 1-bit Comparator design and Energy Estimation using Quantum Dot Cellular Automata”, Int J Eng and Appl Phys, vol. 1, no. 2, pp. 103–110, May 2021.

Issue

Section

Articles