Optimal of 1-bit Comparator design and Energy Estimation using Quantum Dot Cellular Automata


  • V. Satyanarayana 1M.Tech Scholar,Department of ECE,Sree Vidyanikethan Engineering College,Tirupati https://orcid.org/0000-0002-0180-2713
  • M. Balaji M.Tech Scholar,Department of ECE,Sree Vidyanikethan Engineering College,Tirupati
  • K. Neelima M.Tech Scholar,Department of ECE,Sree Vidyanikethan Engineering College,Tirupati


Quantum dots, Cellular Automata, Comparator, Quantum cells, Edge computing


Performance of CMOS technology has been affected in nanosystems due to power dissipation, area, and reliability functionalities. A research initiative which investigates other possible systems with related capacities is QCA. In this paper, QCA nanotechnology was used to create a 1-bit comparator. These circuits are easy to create and do not require any crossovers. The proposed design is extremely efficient in terms of area, cell count, quantum cost and delay, which improves the performance in the range of 74.81% to 99.87%  in terms of quantum cost. As a result, proposed designs are often found in various digital logics that require a small amount of space and low power consumption.


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How to Cite

V. Satyanarayana, M. . Balaji, and K. . Neelima, “Optimal of 1-bit Comparator design and Energy Estimation using Quantum Dot Cellular Automata”, international journal of engineering and applied physics, vol. 1, no. 2, pp. 103–110, May 2021.